TODD A. SIMONDS
20 Comstock Bridge Road, Colchester, CT
860-639-9651
todd@innovative-digital-design.com
CAREER OBJECTIVE:
Seeking a position with the opportunity to best utilize my electronic hardware, firmware, and software design engineering capabilities in a strong contributor or leadership position.
SUMMARY:
EDUCATION:
UNIVERSITY OF CONNECTICUT, Storrs, CT. Electrical Engineering major, instrumentation and hardware design concentration. Graduated in 1991 with a BSEE, 3.6/4.0 GPA.
RENNSELAER POLYTECHNIC INSTITUTE, Hartford, CT. Computer Science major, obtained 12 credits towards a MSCS, 4.0/4.0 GPA.
EXPERIENCE:
VBRICK SYSTEMS, INC. Wallingford, CT. www.vbrick.com 2001-2008
Developed system architecture for micro-TCA based Video Network Appliance and Shelf, capable of H.264 and Windows Media encoding. Performed hardware/software/cost tradeoffs and led interdisciplinary team architecture discussions. Designed complex high-speed printed circuit boards using DSPs, other processors, FPGAs, PCI, gigabit Ethernet, and analog audio/video interfaces. Evaluated hardware and/or software solutions, such as TI DaVinci DM648, DM6446, and DM6467.
Experienced with Linux-based development systems and with VxWorks RTOS. Debugged and resolved several system-level issues and PCI issues that could have been caused by either hardware or software. Exposed problems with TI and Freescale devices and initiated work-arounds.
Designed a 6-million gate FPGA design, a massively parallel compute engine for a proprietary motion estimation algorithm. Led design team of 3 Firmware engineers through design and verification to completion. Design used a Xilinx XC4VLX60 FPGA, with interface and arbiter to two banks of DDR2-400 SDRAM, video input for ITU.656, SMPTE-274M, or SMPTE-296M, dual-port ram and DSP EMIF interfaces. Used advanced floorplanning techniques to meet timing and area constraints. Enabled H.264 ¼-pel motion estimation for HD, and 5 reference frames for D1 resolution. Participated in research SBIR grant.
Led interdisciplinary team through design and deployment of Windows Media encoder using Freescale PowerPC MPC8313 and TI DM642. Developed system architecture for next-generation expandable product based on TI DaVinci DM6446.
Explored several system architectures for video compression, including evaluating performance of various DSPs, microprocessors, and programmable logic, and performing trade-offs between hardware, software, and FPGA firmware development. Developed architecture with hardware/software/firmware partitioning for proprietary phase correlation motion vector algorithm and other portions of the H.264 encoding algorithm.
Lead interface between hardware and software groups during development of MPEG2 and MPEG4 products. Determined root cause and solution of problems whose origins may have been either hardware, firmware, or software. Debugged various low-level software initialization problems under VxWorks RTOS, such as PCI enumeration and memory allocation.
Prototyped design of PCI-to-local-to-PCI PLX bridge to allow new encoding retrofit in legacy systems. Wrote low-level driver and test code in C++ and progressed to a working prototype. Designed PCI memory expansion card w/SDRAM controller. Wrote initialization code in C. Ported C++ JPEG algorithm to PowerPC processor.
Introduced the company to Verilog HDL and hierarchical HDL-based FPGA design. Provided ongoing training in FPGA design using Verilog HDL. Created libraries for hierarchical verilog source code to be simultaneously used by multiple FPGA designs. Used PVCS to archive and track all source modifications.
Architect for MPEG4 Encoder and Decoder FPGA designs, using Xilinx XC2S300E. Organized FPGA hierarchy for simultaneous design with multiple engineers. Designed SDRAM controllers operating at 150MHz. Optimized critical 150MHz circuits for speed using multi-stage pipelining. Locked timing of 150MHz circuits using placement constraints. Developed verilog code for video capture of ITU.601, video encoding to ITU.656, and bus arbitration. Designed output logic for transferring Y/Cb/Cr video data into SDRAM frame buffers. Designed digital sync filter in firmware to enable system operation with non-conforming video signals. Reviewed and modified others' designs to ensure synchronous and reliable design practices. Utilized Xilinx ISE and ChipScope software for design and debugging. Received training on FPGA-embedded microcontrollers using Xilinx EDK software.
Designed MPEG2 Encoder Card with Xilinx XC2S50 FPGA, 108MHz SDRAM, audio and video interface ICs. Responsible for product from design concept through all hardware and software debugging and EMI. Performed schematic capture with Orcad. Designed several other customer-specific prototypes, using TI DM642&6203 DSPs, Motorola 8245 PowerPC, Ethernet MAC/PHY, analog video and audio interfaces, and Xilinx FPGAs, optimizing cost and size.
Developed prototype firmware in XC2S600E FPGA for calculation of motion vectors in a massively parallel fashion. Enabled encoding of H.264 Main Profile standard at D1 resolution. Verified complicated design using verilog test benches and C test code. Modified H.264 reference encoder software in C++ to use external FPGA for hardware acceleration of computation of motion vectors.
Converted various FPGA & CPLD designs from ABEL to Verilog HDL, including Lattice Mach IIs and XC95288XLs.
Developed Video Scaling and Re-Interlacing algorithms. Implemented in TI 6203 DSP assembly code and optimized assembly code for best performance.
Uncovered Xilinx manufacturing defect with Spartan II block ram- provided evidence and test patterns to Xilinx for screening and resolution of root cause.
Resolved existing intermittent issues by improvement of system AC power line noise immunity beyond standard agency approvals.
UNITED TECHNOLOGIES CORPORATION, Otis Elevator Company, Farmington, CT. 1989-2000
LEAD HARDWARE/SOFTWARE
DEVELOPMENT ENGINEER
Design of embedded microprocessor based control board, including 225 MHz MIPS CPU, PCI bus, 10/100 BaseT Ethernet MAC/PHY, South Bridge, USB, CAN to PCI ASIC, flash memory, 75 MHz SDRAM. Cadence Concept, Allegro, and Verilog-XL used for schematic capture, pcb layout, and digital simulation. Debugged low-level software and device drivers using Windows CE operating system. Modeled signal integrity with SpecctraQuest.
Firmware Design of state machines, interfaces, and FIFOs implemented with Xilinx 9536, 95144XL, 9572XL CPLDs, XCS10XL, 4062XLA FPGAs, using Verilog HDL. Synplicity Synplify and Verilog-XL for synthesis and simulation. Conceptualized ASIC (PCI, SSI, USB, CAN, interrupt controller, etc.) using Verilog and various cores (IP), to be prototyped in Xilinx Virtex FPGA.
Developed DSP Software for real-time motor control using a solid-state high-current VF drive, utilizing a 100ms control loop. Developed and optimized assembly code for Motorola 24-bit fixed-point DSPs (56002,56303). Designed and verified control algorithms using Matlab.
Performed elevator system level design; interfacing mechanical, embedded electronic, electrical, and software components. Resolved many existing system-level defects in the field, with troubleshooting and analysis to root cause and correction at the circuit board or system level.
Invented novel position sensing devices and algorithms. Inventor of U.S. Patent # 6,401,875 "Absolute Position Sensing Method and Apparatus for Synchronous Elevator Machines By Detecting Stator Iron Saturation"
Lead engineering team in development of VF Drive Processor Board; Responsible for project management issues for hardware/software design team. Performed all hardware design of an embedded dual processor CPU board, including Motorola 56002 DSP, Intel 80C186EC, and various peripherals. Perfected signal integrity and EMI for an extremely reliable end-product.
Assisted in design of Otis VF Drive ASIC, schematic-based gate array with some blocks in VHDL. Schematic capture, VHDL synthesis and simulation performed with ViewLogic tools. Utilized Motive for static timing analysis. Prototyped ASIC in several Actel 1280 FPGAs. Completely responsible for re-targeting ASIC design to another vendor, from vendor selection through T0 and final verification.
Created several embedded microcontroller designs, developing hardware and coding software. Embedded devices interfaced to various analog and digital sensors. 8051 and 8088 micros used. Performed simulation of sensor interfaces and communication links using PSpice. Completed analog and digital design of various pc boards for AC power monitoring, discrete I/O, and communication links.
Experienced with firmware design since early programmable logic, consolidating discrete logic into standard PLDs and assisting in a digital design using Altera EP910 EPLDs.